View ADC1004S030_5396956.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the ADC1004S030/040/050 are a family of 10-bit high-speed low-power analog-to-digital converters (adc) for professional video and other applications. they convert the analog input signal into 10-bit binary-coded digital signals at a maximum sampling rate of 50 mhz. all digital inputs and outputs are transistor-transistor logic (ttl) and cmos compatible, although a low-level sine wave clock input signal is allowed. the device requires an external source to drive its reference ladder. if the application requires that the reference is driven via internal sources, nxp semiconductors recommends you use one of the adc1003s030/040/050 family. 2. features n 10-bit resolution n sampling rate up to 50 mhz n dc sampling allowed n one clock cycle conversion only n high signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 mhz full-scale input at f clk = 40 mhz) n no missing codes guaranteed n in-range (ir) cmos output n ttl and cmos levels compatible digital inputs n 3 v to 5 v cmos digital outputs n low-level ac clock input signal allowed n external reference voltage regulator n power dissipation only 175 mw (typical) n low analog input capacitance, no buffer ampli?er required n no sample-and-hold circuit required 3. applications n video data digitizing n radar n transient signal analysis n sd modulators n medical imaging n barcode scanner n global positioning system (gps) receiver ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz rev. 03 7 august 2008 product data sheet
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 2 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz n cellular base stations 4. quick reference data 5. ordering information table 1. quick reference data v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shorted together; t amb = 0 c to +70 c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v; v i(a)(p-p) = 2.0 v;c l = 15 pf and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 5.25 v i cca analog supply current - 18 24 ma i ccd digital supply current - 16 21 ma i cco output supply current f clk = 40 mhz; ramp input - 12ma inl integral non-linearity f clk = 40 mhz; ramp input - 0.8 2.0 lsb dnl differential non-linearity f clk = 40 mhz; ramp input - 0.5 0.9 lsb f clk(max) maximum clock frequency ADC1004S030ts 30 - - mhz adc1004s040ts 40 - - mhz adc1004s050ts 50 - - mhz p tot total power dissipation f clk = 40 mhz; ramp input - 175 247 mw table 2. ordering information type number package sampling frequency (mhz) name description version ADC1004S030ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 30 adc1004s040ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 40 adc1004s050ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 50
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 3 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 6. block diagram fig 1. block diagram 12 dgnd2 6 8 r lad 7 9 rb rm rt v i 11 v ccd2 3 26 v cca 21 22 23 24 20 d4 d5 d6 d7 d8 19 18 25 2 d3 d2 17 d1 16 d0 d9 in-range latch cmos outputs latches clock driver 014aaa336 1 clk 10 oe tc ADC1004S030/040/050 13 v cco 4 agnd analog ground digital ground digital ground 27 dgnd1 14 ognd output ground analog voltage input data outputs lsb msb 28 v ccd1 ir output analog - to - digital converter cmos output
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 4 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration adc1004s 050ts clk v ccd1 tc dgnd1 v cca ir agnd d9 n.c. d8 rb d7 rm d6 v i d5 rt d4 oe d3 v ccd2 d2 dgnd2 d1 v cco d0 ognd n.c. 014aaa337 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 table 3. pin description symbol pin description clk 1 clock input tc 2 twos complement input (active low) v cca 3 analog supply voltage (5 v) agnd 4 analog ground n.c. 5 not connected rb 6 reference voltage bottom input rm 7 reference voltage middle vi 8 analog input voltage rt 9 reference voltage top input oe 10 output enable input (cmos level input, active low) v ccd2 11 digital supply voltage 2 (5 v) dgnd2 12 digital ground 2 v cco 13 supply voltage for output stages (3 v to 5 v) ognd 14 output ground n.c. 15 not connected d0 16 data output; bit 0 (least signi?cant bit (lsb)) d1 17 data output; bit 1 d2 18 data output; bit 2 d3 19 data output; bit 3
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 5 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 8. limiting values [1] the supply voltages v cca , v ccd and v cco may have any value between - 0.3 v and +7.0 v provided that the supply voltage differences d v cc are respected. 9. thermal characteristics d4 20 data output; bit 4 d5 21 data output; bit 5 d6 22 data output; bit 6 d7 23 data output; bit 7 d8 24 data output; bit 8 d9 25 data output; bit 9 (most signi?cant bit (msb)) ir 26 in-range data output dgnd1 27 digital ground 1 v ccd1 28 digital supply voltage 1 (5 v) table 3. pin description continued symbol pin description table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage [1] - 0.3 +7.0 v v ccd digital supply voltage [1] - 0.3 +7.0 v v cco output supply voltage [1] - 0.3 +7.0 v d v cc supply voltage difference v cca - v ccd - 0.1 +1.0 v v cca - v cco - 0.1 +4.0 v v ccd - v cco - 0.1 +4.0 v v i input voltage referenced to agnd - 0.3 +7.0 v v i(clk)(p-p) peak-to-peak clock input voltage referenced to dgnd -v ccd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb ambient temperature - 40 +85 c t j junction temperature - 150 c table 5. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 110 k/w
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 6 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 10. characteristics table 6. characteristics v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shorted together; t amb =0 cto+70 c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v; c l = 15 pf and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 5.25 v d v cc supply voltage difference v cca - v ccd - 0.20 - +0.20 v v cca - v cco - 0.20 - +2.25 v v ccd - v cco - 0.20 - +2.25 v i cca analog supply current - 18 24 ma i ccd digital supply current - 16 21 ma i cco output supply current f clk = 40 mhz; ramp input -12ma p tot total power dissipation f clk = 40 mhz; ramp input - 175 247 mw inputs clock input clk (referenced to dgnd) [1] v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v clk = 0.8 v - 1-+1 m a i ih high-level input current v clk = 2 v - 2 10 m a z i input impedance f clk = 40 mhz - 2 - k w c i input capacitance - 2 - pf inputs oe and tc (referenced to dgnd); see t ab le 8 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v il = 0.8 v - 1-- m a i ih high-level input current v ih = 2 v - - 1 m a vi (analog input voltage referenced to agnd) i il low-level input current v i = v rb = 1.3 v - 0 - m a i ih high-level input current v i = v rt = 3.67 v - 35 - m a z i input impedance f i = 4.43 mhz - 8 - k w c i input capacitance - 5 - pf reference voltages for the resistor ladder; see t ab le 7 v rb voltage on pin rb 1.2 1.3 2.45 v v rt voltage on pin rt 3.2 3.67 v cca - 0.8 v v ref(dif) differential reference voltage v rt - v rb 2.0 2.37 3.0 v i ref reference current v rt - v rb = 2.37 - 9.7 - ma
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 7 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz r lad ladder resistance - 245 - w tc rlad ladder resistor temperature coef?cient - 456 - m w /k v offset offset voltage bottom; v rt - v rb = 2.37 [2] - 175 - mv top; v rt - v rb = 2.37 [2] - 175 - mv v i(a)(p-p) peak-to-peak analog input voltage [3] 1.7 2.02 2.55 v digital outputs d9 to d0 and ir (referenced to ognd) v ol low-level output voltage i ol = 1 ma 0 - 0.5 v v oh high-level output voltage i oh = - 1 ma v cco - 0.5 - v cco v i o output current in 3-state mode; 0.5 v < v o ADC1004S030ts 30 - - mhz adc1004s040ts 40 - - mhz adc1004s050ts 50 - - mhz t w(clk)h high clock pulse width full effective bandwidth 8.5 - - ns t w(clk)l low clock pulse width full effective bandwidth 5.5 - - ns analog signal processing linearity inl integral non-linearity f clk = 40 mhz; ramp input - 0.8 2.0 lsb dnl differential non-linearity f clk = 40 mhz; ramp input - 0.5 0.9 lsb e offset offset error middle code; v rb = 1.3 v; v rt = 3.67 v - 1 - lsb e g gain error from device to device; v rb = 1.3 v; v rt = 3.67 v [4] - 0.1 - % bandwidth (f clk = 40 mhz) b bandwidth full-scale sine wave [5] - 15 - mhz 75 % full-scale sine wave - 20 - mhz small signal at mid-scale; v i = 10 lsb at code 512 - 350 - mhz table 6. characteristics continued v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shorted together; t amb =0 cto+70 c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v; c l = 15 pf and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 8 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz t s(lh) low to high settling time full-scale square wave; see figure 6 [6] - 1.5 3.0 ns t s(hl) high to low settling time - 1.5 3.0 ns harmonics (f clk = 40 mhz); see figure 7 and 8 a 1h ?rst harmonic level f i = 4.43 mhz - - 0 db a 2h second harmonic level f i = 4.43 mhz - - 75 - 65 db a 3h third harmonic level f i = 4.43 mhz - - 72 - 65 db thd total harmonic distortion f i = 4.43 mhz - - 64 - db signal-to-noise ratio; see figure 7 and 8 [7] s/n signal-to-noise ratio full scale; without harmonics; f clk = 40 mhz; f i = 4.43 mhz 55 58 - db effective bits; see figure 7 and 8 [7] enob effective number of bits ADC1004S030ts; f clk =30mhz f i = 4.43 mhz - 9.4 - bit f i = 7.5 mhz - 9.1 - bit adc1004s040ts; f clk =40mhz f i = 4.43 mhz - 9.4 - bit f i = 7.5 mhz - 9.0 - bit f i = 10 mhz - 8.9 - bit f i = 15 mhz - 8.1 - bit adc1004s050ts; f clk =50mhz f i = 4.43 mhz - 9.3 - bit f i = 7.5 mhz - 8.9 - bit f i = 10 mhz - 8.8 - bit f i = 15 mhz - 8.0 - bit two-tone intermodulation [8] a im intermodulation suppression f clk = 40 mhz - - 69 - db bit error rate ber bit error rate f clk = 40 mhz; f i = 4.43 mhz; v i = 16 lsb at code 512 -10 - 13 - times/samples differential gain [9] g dif differential gain f clk = 40 mhz; pal modulated ramp - 0.8 - % table 6. characteristics continued v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shorted together; t amb =0 cto+70 c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v; c l = 15 pf and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 9 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz [1] in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. [2] analog input voltages producing code 0 up to and including code 1023: a) v offset bottom is the difference between the analog input which produces data equal to 00 and the reference voltage on pin rb (v rb ) at t amb = 25 c. b) v offset top is the difference between the reference voltage on pin rt (v rt ) and the analog input which produces data outputs equal to code 1023 at t amb = 25 c . [3] in order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the c onverter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins rb and rt via offset resistors r ob and r ot as shown in figure 3 . a) the current ?owing into the resistor ladder is and the full-scale input range at the converter, to cover code 0 to 1023 is b) since r l , r ob and r ot have similar behavior with respect to process and temperature variation, the ratio will be kept reasonably constant from device to device. consequently, the variation of the output codes at a given input voltag e depends mainly on the difference v rt - v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] [5] the analog bandwidth is de?ned as the maximum input sine wave frequency which can be applied to the device. no glitches grea ter than 2 lsb, neither any signi?cant attenuation are observed in the reconstructed signal. [6] the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale i nput (square wave signal) in order to sample the signal and obtain correct output data. differential phase [9] j dif differential phase f clk = 40 mhz; pal-modulated ramp - 0.4 - deg timing (f clk = 40 mhz; c l = 15 pf); see figure 4 [10] t d(s) sampling delay time - 3 - ns t h(o) output hold time 4 - - ns t d(o) output delay time v cco = 4.75 v - 10 13 ns v cco = 3.15 v - 12 15 ns c l load capacitance - - 15 pf 3-state output delay times; see figure 5 t dzh ?oat to active high delay time - 5.5 8.5 ns t dzl ?oat to active low delay time -1215ns t dhz active high to ?oat delay time -1924ns t dlz active low to ?oat delay time -1215ns table 6. characteristics continued v cca = v3 to v4 = 4.75 v to 5.25 v; v ccd = v11 to v12 and v28 to v27 = 4.75 v to 5.25 v; v cco = v13 to v14 = 3.0 v to 5.25 v; agnd and dgnd shorted together; t amb =0 cto+70 c; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v; c l = 15 pf and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit i v rt v rb C r ob r l r ot ++ ---------------------------------------- = v i r l i l r l r ob r l r ot ++ ---------------------------------------- v rt v rb + () 0.852 v rt v rb C () == = r l r ob r l r ot ++ ---------------------------------------- e g v 1023 v 0 C () v ip p C () C v ip p C () -------------------------------------------------------- - 100 =
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 10 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz [7] effective bits are obtained via a fast fourier transform (fft) treatment taking 8000 acquisition points per equivalent funda mental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conve rsion to signal-to-noise ratio: sinad = enob 6.02 + 1.76 db. [8] intermodulation measured relative to either tone with analog input frequencies of 4.43 mhz and 4.53 mhz. the two input signa ls have the same amplitude and the total amplitude of both signals provides full-scale to the converter. [9] measurement carried out using video analyzer vm700a, where the video analog signal is reconstructed through a digital-to-ana log converter. [10] output data acquisition: the output data is available after the maximum delay time of t d(max) . for 50 mhz version nxp semicocnductors recommends the lowest possible output load. 11. additional information relating to t ab le 6 fig 3. explanation of t ab le 6 , t ab le note 3 014aaa325 rt rb rm r lad r ot r l r l r l r l i l r ob code 1023 code 0 table 7. output coding and input voltage (typical values; referenced to agnd, v rb = 1.3 v, v rt = 3.67 v) code v i(a)(p-p) (v) ir binary outputs d9 to d0 twos complement outputs d9 to d0 under?ow < 1.475 0 00 0000 0000 10 0000 0000 0 1.475 1 00 0000 0000 10 0000 0000 1 - 1 00 0000 0001 10 0000 0001 - 1022 - 1 11 1111 1110 01 1111 1110 1023 3.495 1 11 1111 1111 01 1111 1111 over?ow > 3.495 0 11 1111 1111 01 1111 1111
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 11 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz table 8. mode selection tc oe d9 to d0 ir x 1 high impedance high impedance 0 0 active; twos complement active 1 0 active; binary active fig 4. timing diagram 014aaa326 clk v i data n - 2 data d0 to d9 data n - 1 data n data n + 1 sample n + 2 sample n + 1 v cco sample n sample n + 2 sample n + 1 sample n t w(clk)h t w(clk)l t d(s) t d(o) t h(o) 50% 0 v v cco 50% 0 v
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 12 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz frequency on pin oe = 100 khz fig 5. timing diagram and test conditions of 3-state output delay time fig 6. analog input settling time diagram low high high low adc1004s050 v ccd v ccd s1 oe oe output data output data 10% 50% 50% 90% 50% t dlz t dzl t dhz t dzh 15 pf 3 . 3 k w s1 test v ccd t dlz v ccd t dzl dgnd t dzh t dhz dgnd 014aaa335 014aaa327 code 1023 code 0 50% 50% clk v i t s(lh) t s(hl) 50% 50% 2 ns 2 ns 0 . 5 ns 0 . 5 ns
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 13 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz effective bits: 9.42; thd = - 71.8 db. harmonic levels (db): 2nd = - 83.19; 3rd = - 78.09; 4th = - 78.72; 5th = - 78.33; 6th = - 77.55. fig 7. typical fast fourier transform (f clk = 40 mhz; f i = 4.43 mhz) 014aaa328 - 60 - 100 - 20 +20 amplitude (db) - 140 f (mhz) 0 20.0 15.0 5.00 10.0 effective bits: 8.91; thd = - 62.96 db. harmonic levels (db): 2nd = - 71.38; 3rd = - 71.54; 4th = - 74.14; 5th = - 65.15; 6th = - 77.16. fig 8. typical fast fourier transform (f clk = 50 mhz; f i = 10 mhz) 0 f (mhz) 20.0 25.0 15.0 5.0 10.0 014aaa329 - 60 - 100 - 20 +20 amplitude (db) - 140
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 14 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz fig 9. cmos data and in-range outputs fig 10. analog inputs fig 11. oe and tc input fig 12. rb, rm and rt 014aaa330 v cco d9 to d0 ir ognd v cca v i agnd 014aaa332 014aaa323 v cco ognd oe tc v cca rt rm rb agnd 014aaa331 r l r l r l r l fig 13. clk input v ccd clk 1 . 5 v dgnd 014aaa324
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 15 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 12. application information 12.1 alternative parts the following alternative parts are also available: [1] pin to pin compatible the analog and digital supplies should be separated and well decoupled a user manual is available that describes the demonstration board that uses the version ADC1004S030/040/050 family with an application environment. (1) rb, rm and rt are decoupled to agnd. (2) pin 15 may be connected to dgnd in order to prevent noise in?uence. (3) decoupling capacitor for supplies; must be placed close to the device. fig 14. application diagram adc1004s050 clk v ccd1 tc dgnd1 v cca ir agnd d9 n.c. d8 rb (1) d7 rm (1) d6 vi d5 rt (1) d4 oe d3 v ccd2 d2 dgnd2 d1 v cco d0 ognd n.c. (2) 014aaa338 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf (3) (3) (3) (3) agnd agnd agnd table 9. alternative parts type number description sampling frequency adc1003s030 single 10 bits adc, with voltage regulator [1] 30 mhz adc1003s040 single 10 bits adc, with voltage regulator [1] 40 mhz adc1003s050 single 10 bits adc, with voltage regulator [1] 50 mhz adc1005s060 single 10 bits adc [1] 60 mhz adc0804s030 single 8 bits adc [1] 30 mhz adc0804s040 single 8 bits adc [1] 40 mhz adc0804s050 single 8 bits adc [1] 50 mhz
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 16 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 13. package outline fig 15. package outline sot341-1 (ssop28) unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150 99-12-27 03-02-19 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 17 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 14. revision history table 10. revision history document id release date data sheet status change notice supersedes ADC1004S030_040_050_3 20080807 product data sheet - ADC1004S030_040_050_2 modi?cations: ? corrections made to the table description in t ab le 1 . ? corrections made to several entries in t ab le 6 . ? corrections made to figure 12 . ADC1004S030_040_050_2 20080616 product data sheet - ADC1004S030_040_050_1 ADC1004S030_040_050_1 20080611 product data sheet - -
ADC1004S030_040_050_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 7 august 2008 18 of 19 nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. quick reference data the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors ADC1004S030/040/050 single 10 bits adc, up to 30 mhz, 40 mhz or 50 mhz ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 7 august 2008 document identifier: ADC1004S030_040_050_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 thermal characteristics. . . . . . . . . . . . . . . . . . . 5 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 additional information relating to t ab le 6 . . . 10 12 application information. . . . . . . . . . . . . . . . . . 15 12.1 alternative parts . . . . . . . . . . . . . . . . . . . . . . . 15 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 18 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 contact information. . . . . . . . . . . . . . . . . . . . . 18 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

▲Up To Search▲

Price & Availability of ADC1004S030

	To Download ADC1004S030 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .